Goldman Sachs wants the most miserable engineers to build a trading platform
If you want to work with the most powerful tech in finance, you probably want to be a hardware engineer working with FPGAs. Goldman Sachs has recruited them in its trading team for some time and is building a new infrastructure team with them, but the work is notoriously difficult.
Goldman's global banking and markets team is recruiting FPGA engineers in London and Stockholm to build a "high-capacity, yet nimble and adaptive FPGA platform for trading equities." It asks for "extensive experience with SystemVerilog" in particular, a language with its fair share of haters.
That's unfortunate because Jane Street developer Andrew Hunter says coding in Verilog is "miserable and unpleasant." Engineers on HackerNews say the language is "fantastically easy to create bugs" with. Dan Luu, an engineer at $1.1 trillion hardware manufacturer NVIDIA for over a decade, says the language is "baroque" with a "counterintuitive" nature that leads to the creation of "unsynthesizable garbage." 😱
There are upsides to this. As with C++ it's perhaps the abundance of faults in the language that makes its elite engineers so desirable. It's also the non-bank firms that want them the most. Aiden Pestell, senior consultant at executive search firm Odin Partners, says "FPGA is massively in demand for most HFT firms globally" due to its unparalleled "nanosecond speed." He refutes the idea that they're miserable, however, saying they "seem happy and love what they do."
FPGA teams are currently very Europe/US focused at banks, but Pestell is expecting them to go global soon. "Banking is going towards FPGA in years to come," Pestell says APAC hardware teams "will catch up in two years or so."
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